Intel Larrabee (GP)GPU project

[Stratos]

Intel má ještě brutálnější marketingové oddělení, než Nvidia, a to je co říct. A v serverový sféře se pohybuje od svého založení.

ani ne tak brutalnejsi jako ze spis na to maji mnohem vic financi to protlacit. Uvidime pristi rok az prejdou na lepsi vyrobni proces co s tim udelaj.

[yuri.cs]

Knights Ferry nafocen


Cely clanek na: cb.de

[del42sa]

zdá se, že Intel projekt Larrabee, respektive software 3D rendering zcela nezavrhl, jak se mnozí domnívali po představení koprocesorů Knights Ferry a Knights Corner. Charlie někde vyčmuchal, že vývoj Larrabee jako GPU stále probíhá http://semiaccurate.com/2012/06/12/what ... s-landing/

[del42sa]

konečně podrobnější info o Larrabee / Phi : http://semiaccurate.com/2012/08/28/inte ... long-last/

[del42sa]

další podrobnosti o Xeon Phi (Larrabee) :

http://www.slideshare.net/IntelXeon/und ... chips-2012

http://news.cnet.com/8301-13924_3-57326 ... core-chip/

[del42sa]

Intel konečně vydal Larrabee aka Xenon Phi. že by nastal soumrak GPGPU ? Velmi zajímavý článek z SA.

DIE:


http://semiaccurate.com/2012/11/13/what ... pu-market/

info o kartě :

přes 5 miliard tranzistorů, zachovány ale vypnuty grafické obvody, 62 jader, takt 1,1 GHz , paměti 5,5 GT/s, 300W TDP.

http://semiaccurate.com/2012/11/12/a-lo ... -hardware/

[DOC_ZENITH]

No, vzhledem k tomu jakou to má cenu a jak snadno se pro to programuje, tak jen blázen by si zvolil cokoliv od AMD. A jen lidé co už dlouho dělaj v cudě či by pro ně Tesla byla citelně rychlejší, tak ti zůstanou u ní. U specializovaných strojů ta otázka snadného programování není tak kritická, ale ten rozdíl v ceně je velkej ve prospěch intelu.

Nicméně, konec GPGPU alespoň jeho skomírání pozorujeme spíš v důsledku toho že desktop grafiky z něj pomalu ustupují, protože se ukázalo že to nikdo nepoužívá a akorát to žere proud a tranzistory. Larabe neni GPU, je to masivní výpočetní karta co se dává do slotu. Takové tu už na různé specifické účely byly v minulosti, a nadále tomu tak bude. Vašemu systému to prostě přidává dodatečný výpočetní výkon pro SW co to umí použít.

Tohle se těžko prosadí do systému u lidí doma, to je nesmyslná úvaha. GPGPU u lidí doma což by byla jediná cesta jak jej masivně prosadit selhalo. Nvidia na něj zanevřela když jej sama do GPU přestala cpát, a AMD to korunovalo tím že jejich APU kde by to člověk nejvíce čekal maj zasaralou architekturu GPU části a jsou proto nevhodné by default.

Larabe je hezká karta do výpočetních center ale ty byly vždy svá kategorie.

[del42sa]

Why is Intel so secretive about Phi’s die?

Ever noticed that Intel is deathly afraid to talk specifics about not-Larrabee Xeon Phi, especially die size? Ever wonder why there are absolutely no pictures of it floating on the net?

SemiAccurate did ask about die sizes, for pictures of unlidded parts, and all the stuff you would think Intel is proud of but forgot to include in the presentations. Luckily for us, the answer we got back is absolutely consistent, not the usual wishy-washy ballpark deflection we are used to. Unfortunately however, that answer was a consistent, “no”. There is a good reason why they are deathly afraid to release this too.

The closest we got to a picture was Thomas Ryan’s shot of a chip in the hand of an Intel spokesmodel. Those models may be chosen for their looks, but they are well trained too, there is nothing to get a size reference from in the picture. It is unquestionably huge, but how large is not discernible. Some people claim it is about 350mm^2 on the Intel 22nm FinFET process, a number that our moles say is laughably low. Unfortunately our moles shut up after they stop giggling.

Intel won’t show any bare boards either, the few shots that are out there have heat sinks or are older versions, quite likely not 22nm silicon either. They all have the PEG connectors off the back, the real boards have them on the top. This ‘minor’ detail is more than enough to question what the pictures are, and then you have to ask what chip is on them.

Luckily, SemiAccurate’s moles have got us a picture, it isn’t stunning quality, think more of what the author takes himself rather than correctly in focus. That said given the circumstances it is amazing he/she/it/they actually snapped it. Well done. With a little pixel counting, the exact die size is… we’ll get to that in a second. That is the least of the news though, there are a lot of interesting details that come from the picture, especially surrounding Haswell.

The first bit you probably care about is the die size. Unfortunately the bare board has a heat spreader on it that completely obstructs the die so we can’t give you any hard numbers. Worse yet the heat spreader is much much larger than the die could possibly be. Take a look at the shot below, blurry it may be, but we can’t find any other anywhere. Once again, thanks to our mole for it.

Phi shot WM Why is Intel so secretive about Phis die?

The bare board shot with Xeon Phi die

Based on pixel counting and comparisons to known size bits on the board, SemiAccurate’s crack team of competitive intelligence experts went to work. They were a bit grumpy that their day job of scraping gum off the sidewalk was rudely interrupted for lesser tasks, but we do pay badly so they counted pixels for weeks while the gum piled up. The results were between 46 and 48mm in length, 36 to 38mm in height for a rough estimate of between 1650-1800mm^2. Yes we did the numbers much closer than that, but given the blurriness 17 digits is rather silly to report. Did you learn nothing in high school science class?

Still a lowball number of 1650mm^2 is a tad higher than the equally farcical 350mm^2 number some are touting. SemiAccurate’s moles say the Knights Corner die is closer to 700mm^2 than 600, but this image sheds no light on that part either. Even a rough estimate of the silicon area is pointless given the disparity between the heat spreader area and Intel’s maximum reticle size. Why use such a massive heat spreader for a chip that isn’t half that area? Spreading heat may seem like the obvious answer but it is unlikely to be the reason. We won’t go into technical details about why, take a night class in thermal management if you really want to know.

Remember in Thomas Ryan’s story he mentioned GDDR5 being on an interposer under the lid? GDDR5 is on the board, but what about L3 or other cache? No one has talked about construction before of after Thomas’ scoop, nor has Intel confirmed or denied anything about it either. That said, we believe it is accurate.

So, any guesses the spreader a large die would need if you stuck it on an interposer and slapped some cache around it? Some cache that doesn’t show up on the spec sheet either, according to Intel all of that is on die and private to the respective core. So what could be there? Why would they not disclose it? The answer to both is probably the same reason that no one can actually buy a Phi on the market, trade secrets/competitive intelligence. I am willing to bet we have found the first time Intel put out some advanced, very very advanced actually, packaging tech.

All of that stuffed under the lid nicely explain the size, secrecy, and likely where all lot of the heat is coming from too. This technological marvel is likely painfully expensive to make too, a massive 22nm die with interposers and whatever else they slapped under the lid isn’t cheap. That said, Xeon Phis start at around $2000 so margins won’t be totally under water, but they are laughable compared to Intel’s GPU based competition.

And that is the real interesting thing we can discern from the picture, the cost. Intel can make transistors with technologies and geometries that no one else can come close to, that is not in doubt. They can package the result in ways that no other company can even attempt at the moment and do it in, err, painfully low volumes. What they can’t do is do it at a decent cost, and that is going to hurt them in the long run. And if Haswell GT3e/Crystalwell uses the same type of construction, what do you think that will mean for pricing? Now do you get it?S|A

[webwalker]

Něco z Twitteru

simonmcs
If the rumoured 50+ PFLOP #XeonPhi system in China is real, we need to start porting all the #CUDA apps to #OpenCL pronto

[Krteq]

Jen doplním, že se jedná o Tianhe-2 SC a Simon je vedoucím katedry mikroelektroniky a přednášejícím pro HPC systémy a jejich architekturu na Bristolské univerzitě.

Pokud by přešel Bristol, troufám si tvrdit že by přešli i další a konečně by mohl nastat soumrak proprietárních standardů.

[del42sa]

David Kanter vydal zajímavý článek na téma Knights Landing.

http://www.realworldtech.com/knights-la ... eculation/

stručný výcuc:

*Knights Landing má být samostatně bootovatelné zařízení. (Larrabe má pouze základní x86 compatibilitu)

*Intel bude musett zřejmě navrhnout zcela nové "custom core" pro KL (jádra Haswell ani Silvermont se pro tuto architekturu nehodí)

*jádra budou navržena na vysokou propustnost (throughput) při zachování vysokého Single Thread výkonu s oddělenou zdvojenou FPU částí (podobně jako u Bulldozeru)

*ondie eRAM (crystallwel)

\\
Nakonec to tedy bude hoodně custom Silvermont jádro

*podpora všech moderních instrukcí MMX, SSE, AES, AVX

*dvě 512 bit FPU jednotky na výpočetní jednotku (compute unit)

*dvě jádra a dvě FPU v jedné CU

*4 threads/jádro

*trojnásobný výkon v FP operacích s dvojitou přesností

*ondie 8 -16 GB MCDRAM + 6-ti kanálový řadič DDR4

*volitelná sběrnice Storm Lake

*nižší TDP



Ve výsledku už tohle nebude mít s původním Larrabee nic společného. Jádro bude úplně nové, přijde o texturovací jednotky a další obvody související s GPU a které jsou stále přítomny v Xeonu Phi....